The present invention relates to CMOS logic in general, and in particular, to CMOS logic including mixed dynamic and static logic types.
Power dissipation in CMOS logic chips is linearly dependent on the switching activity in the logic circuits on the chip. In the static state, CMOS logic dissipates almost no power. However, when a CMOS circuit switches between logic states, power is dissipated. Thus, as the frequency of switching between logic states increases, the power dissipated in a CMOS logic circuit increases in direct proportion to the switching frequency.
This switching activity is dependent on the input signal supplied, the logic function implemented, and the circuit type used as the switching activity in static logic circuits and in dynamic logic circuits differs even when the same logic function is implemented. Moreover, the clock circuits themselves consume power in the transition between the phases of the clock. However, the switching activity of the clock circuits is constant and always is equal to two transitions per clock cycle. In other words, the switching frequency of the clock circuits is always twice the clock frequency itself.
In order to determine the power dissipation in a logic chip, it is therefore necessary to account for the switching activity of the logic circuits constituting the logic chip. This complicates the design of logic chips employing mixed static CMOS logic circuits and dynamic CMOS logic circuits.
Static logic is designed under a constraint that logic signals change state no more than once per clock cycle. That is, in a logic circuit consisting entirely of static CMOS circuits, all switching, is xe2x80x9cvisible,xe2x80x9d i.e., directly apparent by a comparison of states at the end of each clock cycle, since an output either transitions once from the preceding clock cycle to the current clock cycle, or does not transition at all. Therefore, for static logic circuits, circuit power can be calculated from one-cycle logic simulations, where the logic state of the circuit is determined at the end of each clock cycle.
For dynamic logic, however, output signals may change more than once per cycle. Therefore, for dynamic logic, switching activity cannot be measured by an analysis based merely on states at the end of each clock cycle. That is, in a dynamic logic circuit, not all switching is visible. Thus, in logic circuits including both dynamic and static circuitry, one-cycle logic simulations, according to the prior art, cannot be used to determine power consumption. Moreover, not only do dynamic elements behave differently than static elements, but static elements behave one way in isolation and another way if the static elements follow dynamic elements. Consequently, computational resources are consumed by the additional simulations required for determining dynamic logic switching activity and mixed, static-dynamic logic switching activity. Also, designers must create different logic models for these simulations, thereby consuming designer resources. Thus, there is a need in the art for methods and apparatus to determine the power consumption in logic circuits including mixed dynamic and static logic elements, without the requirement that each clock transition be simulated.
The previously mentioned needs are addressed with the present invention. Accordingly, there is provided, in a first form, a method of determining power consumption in a logic device. The method includes the steps of inputting first and second tagged logic signals, wherein a tag has a first predetermined value if the input signal has dynamic behavior and a second predetermined value if the input signal has static behavior, and wherein the first logic signal constitutes a logic state of the logic device in a current cycle and the second logic signal constitutes a logic state in a previous cycle. The method also includes determining a number of switching transitions from the first and second tagged logic signals, and outputting a power consumption value, wherein the power consumption value is formed from a per transition power consumption value multiplied by a clock signal frequency further multiplied by the number of switching transitions.
In another embodiment, the method includes the steps of determining a Boolean circuit behavior signal of the logic device in response to a plurality of clock edge tags and corresponding plurality of output transition logic signals, inputting first and second logical output signals of the logic device wherein the first and second output signals constitute a logical state of the logic device in a current cycle and a previous cycle, respectively. The method also includes the step of determining a number of transitions of the logic device in the current cycle from the Boolean circuit behavior signal and the first and second logical output signals. The step of outputting a power consumption value includes multiplying a per transition power consumption value by a clock signal frequency and further multiplying the product by the number of transitions.
There is also provided, in a second form, a data processing system. The data processing system includes circuitry operable for inputting first and second tagged logic signals, wherein a tag has a first predetermined value if any input signal has dynamic behavior and a second predetermined value if the input signal has static behavior, and wherein the first logic signal comprises a logic state of a logic device in a current cycle and the second logic signal comprises a logic state in a previous cycle. The data processing system further includes circuitry operable for determining a number of transitions from the first and second tagged logic signals, and circuitry operable for outputting a power consumption value, wherein the power consumption value is formed from a per transition power consumption value multiplied by a clock signal frequency further multiplied by the number of transitions.
In another embodiment, the data processing system contains circuitry operable for determining a Boolean circuit behavior signal of the logic device in response to a plurality of clock edge tags and a corresponding plurality of output transition logic signals, and circuitry operable for inputting first and second logical output signals of the logic device wherein the first and second output signals constitute a logical state of the logic device in a current cycle and a previous cycle, respectively. The data processing system also contains circuitry operable for determining a number of transitions of the logic device in the current cycle from the Boolean circuit behavior signal and the first and second logical output signals, and circuitry operable for outputting a power consumption value, wherein the power consumption value is formed from a per transition power consumption value multiplied by a clock signal frequency further multiplied by the number of transitions.
Additionally, there is provided, in a third form, a program product adaptable for storage on a program storage media, the program product operable for determining power consumption in a logic device. The program product includes programming for inputting first and second tagged logic signals, wherein a tag has a first predetermined value if the input signal has dynamic behavior and a second predetermined value if the input signal has static behavior, and wherein the first logic signal constitutes a logic state of the logic device in a current cycle and the second logic signal constitutes a logic state in a previous cycle, and programming for determining a number of switching transitions from the first and second tagged logic signals. The program product further includes programming for outputting a power consumption value, wherein the power consumption value is formed from a per transition power consumption value multiplied by a clock signal frequency further multiplied by the number of switching transitions.
In another embodiment, the program product adaptable for storage on a program storage media, includes programming for determining a Boolean circuit behavior signal of the logic device in response to a plurality of clock edge tags and corresponding plurality of output transition logic signals, and programming for inputting first and second logical output signals of the logic device wherein the first and second output signals constitute a logical state of the logic device in a current cycle and a previous cycle, respectively. The program product further includes programming for determining a number of transitions of the logic device in the current cycle from the Boolean circuit behavior signal and the first and second logical output signals, and programming for outputting a power consumption value, wherein the power consumption value is formed from a per transition power consumption value multiplied by a clock signal frequency further multiplied by the number of transitions.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.